ameed
Advanced Member level 4
hi all,
For a small Full custom design, a designer who is fully aware of the DFM issues can do his bit to increase the yield. But finally in a big chip design the designer has to be dependent on the EDA tools to do this.
Most of the EDA companies have come out with tools which take care of these DFM issues. But the universal success of such tools is still unknown!!
I think with other constraints taking priority over DFM issues, designers at this moment are not really worried about such problems. That is why fixing the DFM issues is "optional" and not "mandatory" at this moment.
But to survive in this competent market , soon DFM issues would be on a higher priority.
thanx.
For a small Full custom design, a designer who is fully aware of the DFM issues can do his bit to increase the yield. But finally in a big chip design the designer has to be dependent on the EDA tools to do this.
Most of the EDA companies have come out with tools which take care of these DFM issues. But the universal success of such tools is still unknown!!
I think with other constraints taking priority over DFM issues, designers at this moment are not really worried about such problems. That is why fixing the DFM issues is "optional" and not "mandatory" at this moment.
But to survive in this competent market , soon DFM issues would be on a higher priority.
thanx.