Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Tackling DFM issues by designers

Status
Not open for further replies.

ameed

Advanced Member level 4
Joined
Jun 28, 2007
Messages
107
Helped
6
Reputation
12
Reaction score
1
Trophy points
1,298
Location
INDIA
Activity points
1,931
hi all,
For a small Full custom design, a designer who is fully aware of the DFM issues can do his bit to increase the yield. But finally in a big chip design the designer has to be dependent on the EDA tools to do this.:D
Most of the EDA companies have come out with tools which take care of these DFM issues. But the universal success of such tools is still unknown!!

I think with other constraints taking priority over DFM issues, designers at this moment are not really worried about such problems. That is why fixing the DFM issues is "optional" and not "mandatory" at this moment.
But to survive in this competent market , soon DFM issues would be on a higher priority.:D

thanx.
 

khotkar

Junior Member level 2
Joined
Jan 30, 2007
Messages
20
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Activity points
1,396
DFM issue

ameed I agree with u.

The Layout designer should take care of DFM.
It is very important of following points:
Yield
Performance
and
life time of chip.

It is slightly increase area and no of chips per wafer is reduce 10% but performance is 99% good.
DFM is very big issue in VLSI.
 

gafsos

Full Member level 4
Joined
Feb 1, 2006
Messages
190
Helped
24
Reputation
48
Reaction score
11
Trophy points
1,298
Location
North Africa
Activity points
2,450
Re: DFM issue

DfM: Design for Manufacturing or Design for Manufacturability: methodology which, when applied to microelectronics, permits to improve the yield/robustness of integrated circuits, taking into account the constraints of manufacturing in the early design phases.

The DfM Guidelines are a set of recommendation for designers.
These guidelines are defined for a given process of a given technology and are highly influenced by the materials, equipment, settings.

As a consequence, the DfM guidelines are based on the engineering judgment of process experts (often using the parametric test results of layout process structures on advanced reticles).

These guidelines are also discussed and reviewed with design experts.
For the 65 nm guidelines for expl , experts from the following areas have participated:
• Back-End process
• Front-End process
• Yield enhancement
• eDRAM design
• Full Custom design
• IO design
• SoC design
• Std cells design
• SRAM/ROM design
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top