Systemverilog vs E language

[cfriend]

which one is better systemverilog or e language

I'm a new one want to verificate my design, but i don't kown which is better one? systemverilog or E language?

 

[jackson_peng]

hehe, probably, it is not depend on the language power, but the simulation tools you have

 

[cfriend]

to jackson_peng:
I have cadence incisive platform which surpport systemverilog and E language, which one is better?

 

[aji_vlsi]

to jackson_peng:
I have cadence incisive platform which surpport systemverilog and E language, which one is better?

Hi,
SV is now an IEEE standard and all 3 major vendors have varied level of support for it today. AFAIK, Cadence has the least for SV-Testbench against Mentor/SNPS. You need to check with your tool documentation. As far as E goes, E is being standardized, but not many vendors seem to be supporting - atleast not the main ones - no SNPS/Mentor. Hence for your case, you may want to start using SV-Design, Assertions - as much as NC supports, and slowly move to SV-Testbench.

HTH
Ajeetha
www.noveldv.com