Systemverilog module in verilog testbench

[mundravale]

verilog bind

Hi,
I was looking for function coverage support in my existing verilog testbench. One way to achieve this is using System verilog coverage constructs. I was wondering if I can write SV coverage constructs under SV program /module and integrate this module inside verilog testbench. Will it work? For SV constructs to be implemented, do we need to have top testbench in SV or verilog 2k will do?

Thanks & Rgds

Dhananjay

 

[aji_vlsi]

sv bind

Dhananjay,
SV covergroup can be inside module/interface/program/class etc. If I understand your setup correctly, you have an existing Verilog TB + DUT and want to add covergroup. Easiest option will be to use SV's bind feature to achieve this.

For instance:

module sv_fcov (input sig_a, sig_b,  sampl_event);

  covergroup my_cg @ (sampl_event);
    c1 : coverpoint sig_a;
    c2 : coverpoint sig_b;
  endgroup : my_cg

 my_cg my_cg_0 = new();
endmodule : sv_fcov

Now assume that your DUT module is named dut_controller and has the signals sig_a, sig_b and sampl_event - then you can use SV bind as:

File: bind.sv

bind dut_controller sv_fcov sv_fcov_0 (.*);

With VCS one can do:

vcs -sverilog bind.sv sv_fcov.sv dut.v -R

Hope this gives you the hint. Feel free to contact me at ajeetha <> gmail.com if you need more. My company specializes in SystemVerilog adoption to our customers based in Bangalore, please see: www.noveldv.com.

Good Luck
Ajeetha, CVC
www.noveldv.com

 

[mundravale]

system verilog module

Hey Ajeetha,

Thanks for your solution. I've exact same setup. Now the only constraint is you should have all signals available in top level TB module port lists that you want to use. Suppose I want to use some signal from submodule then that signal has to bring out to top though corresponding module port list. Right?


Thanks again,

Dhananjay

 

[aji_vlsi]

bind verilog

Hey Ajeetha,

Thanks for your solution. I've exact same setup. Now the only constraint is you should have all signals available in top level TB module port lists that you want to use. Suppose I want to use some signal from submodule then that signal has to bring out to top though corresponding module port list. Right?


Thanks again,

Dhananjay

Dhananjay,
Glad to be of assistance.

Now the only constraint is you should have all signals available in top level TB module port lists that you want to use. Suppose I want to use some signal from submodule then that signal has to bring out to top though corresponding module port list. Right?

No not really true. SV Bind attaches to the target module - in my example "dut_controller". Say it is instantiated under:

top_tb.dut.block_1.control_0

Even then it will work - that's the beauty of SV bind. If you have signals in submodule that are inside dut_controller, you can use regaul XMR as if you are inside dut_controller scope.

Try it out and let me know of any issues.

Regards
Ajeetha, CVC
www.noveldv.com