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SystemVerilog Model Design

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Maulik Suthar

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Hello all,

I am currently working on a model design for a memory, that memory has 32 independent ports and also has control signals and other stuff.
I want to implement a class based model in which i can write and read into a memory from 32 channels which run parallel to each other but the changes in one channel should be available to others also. whenever there is a config cycle they should listen to one master channel and have to get the proper control signals accordingly. can anyone give me a start to how to make a class that can be used for 32 channels and can do independent operations.
Thank You
 

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