Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

SystemVerilog Model Design

Status
Not open for further replies.

Maulik Suthar

Newbie level 3
Newbie level 3
Joined
Jul 16, 2013
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Visit site
Activity points
26
Hello all,

I am currently working on a model design for a memory, that memory has 32 independent ports and also has control signals and other stuff.
I want to implement a class based model in which i can write and read into a memory from 32 channels which run parallel to each other but the changes in one channel should be available to others also. whenever there is a config cycle they should listen to one master channel and have to get the proper control signals accordingly. can anyone give me a start to how to make a class that can be used for 32 channels and can do independent operations.
Thank You
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top