I'd like to eliminate assignment of signals to every single instantiation of the interface -- see comments [1] and [2] in topmost code snippet. What is the best way to accomplish this? One way is to assign signal to a common interface and then use this common interface to connect to the other two interfaces -- need to try this out.
Code:
module top (
input [1:0] in,
output [2:0] out
);
//wires and registers
wire [1:0] module_a_out;
wire [1:0] module_b_out;
//IO assignments
assign out = module_a_out | module_b_out;
Myinterface Myif1();
Myinterface Myif2();
//[1]interface 1 to module a -- better way to accomplish this?
assign Myif1.in = in;
assign module_a_out = Myif1.out
//[2]interface 2 to module b -- better way to accomplish this?
assign Myif2.in = in;
assign module_b_out = Myif2.out
module_a module_a (.my_if_s(Myif1));
module_b module_b (.my_if_s(Myif2));
endmodule
1. I'm trying to avoid any combination logic in the interface. I'm assuming wor would get synthesized into an OR gate.
2. What happens when a different signal from a different bus acts as a select? For example:
Code:
always_comb begin
if(my_another_if.select == 11) begin
myif.out = myif1.out;
end
else if(my_another_if.select == 10) begin
myif.out = myif2.out;
end
else begin
myif.out = 2'd9;
end
end
I was thinking about breaking up the interface into 4 different interfaces as shown below. Should I be worried about using this technique ? I want to use this because I can eliminate assigning each and every input from top interface to multiple slave interface. I can do this because I'm separating the input and output part of the slave interface.
And, when it comes to the slave outputs (and top level slave output), I could pass it up to the top and use the above code to get my final slave output. Am I defeating the purpose of using interfaces by using it in weird ways? And there are no mod-ports in these interface definitions. Is that a bad thing? I haven't used interfaces before. I'm afraid that as the code grows, I'll have to rethink my whole approach.