Systemverilog for hardware design

[osm3000]

Hi All,

Why Systemverilog isn't widely used - at least from what I can see - in hardware design - not just verification -?

It seems to me that it offers much better constructs and abstractions over Verilog.

 

[dave_59]

But it is. SystemVerilog for RTL is approaching 50% of non-FPGA designs. Pure Verilog usage has begun to decline and VHDL has remained relatively flat. See this study from 2012.

The main barriers for SystemVerilog adoption are the free synthesis tools supplied by the FPGA vendors. Although some vendors have made significant progress in their support of SystemVerilog, designers are reluctant to use features that may not be supported should they need to switch vendors. It will come, eventually.

And as much as we engineers love to develop the latest and greatest technologies, we are very reluctant to adopt the latest and greatest technologies used in the development process. We stick with what we know works. Just look at one the the most productive features of Verilog-2001: the ANSI style port lists that lets you declare a port by mentioning it once instead of up to 3 times using the Verilog-1995 syntax. Yet people in college are still being taught the 1995 syntax.

 

[osm3000]

Hi Dave,

Many thanks for your reply.

I read the study you mentioned, really interesting.

Concerning your point about the non-availability of synthesis tools supplied by the FPGA vendors, I want to mention that there's also no free simulation tool for systemverilog, yet it's widely adopted in verification, more than any other language according to the study you mentioned. I believe also that Xilinx Vivado suit and Altera Quarts are now both supporting systemverilog for FPGA design.

I do totally agree our reluctance to adopt new technology in the development process - also I believe it's more dependent on the flexibilty of the managers, and their willing to step out of the safe zoon -.

 

[dave_59]

Hi Dave,

I want to mention that there's also no free simulation tool for systemverilog

Not true. Modelsim Altera Starter Edition is free and supports the fully synthesizable subset of SystemVerilog for design, and most of the class-based verification features. It does not support constrained random stimulus, functional coverage or assertions.

Yes, Xilinx Vivado just last year added support for many SystemVerilog features for synthesis, maybe 2/3rds of it, but their free simulator does not support any SystemVerilog.

I haven't seen anyone do a survey of what's available in both FPGA vendors synthesis tools, but I'm guessing the intersection of SystemVerilog support between both is still very low.

 

[osm3000]

Hi Dave,

Sorry, I meant that there's no current free simulation tool for systemverilog for verification. As you mentioned, many systemverilog features in "Modelsim Altera Starter Edition" aren't supported.

Yet, with this considered, that no free tool is available, people are using it in an increasing way.

I believe that - as you mentioned - "designers are reluctant to use features that may not be supported should they need to switch vendors". But without doubt, this gap will be closed eventually.