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SystemVerilog Assertions

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ned_zeppelin

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Hi,

I have started using assertions recently, and there is a relatively common case I can't seem to figure out the correct syntax for. Hopefully, someone in here can help me.

The basic idea can be illustrated by a short example:


Code Verilog - [expand]
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property p1;
@(posedge clk) 
$rose(sig1) |->
[0:$] $fell(sig2)
##1 $fell(sig1)
endproperty



But I also want to check that, lets say $fell(sig3), does not happen before [0:$] $fell(sig2). I have tried some variations of not, and, intersect etc. without any luck. Does anyone know how/if this can be done?

Any help is greatly appreciated.
 
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