systemverilog assertion

[shahsanket24]

hello to all..

i want to write assertion for following condition.
bit [3:0] x;
bit [5:0] count;
whenever x is 4 then i want to check count =7, whenever x=6 i want to check count=9,whenever x=7 i want to check count=11. please help urgently

 

[dave_59]

That looks like three separate properties
property p1;
x == 4 |-> count == 7;
endproperty
property p2;
x == 6 |-> count == 9;
endproperty
property p3;
x == 7 |-> count == 11;
endproperty

assert property (@(posdge clk) (p1 and p2 and p3));

 

[shahsanket24]

Thanks Dave Rich.......
I have tried with this but it is unnecessary firing assertion even one of the condition is true at that point what i want is any of the condition should be checked for example if x=4 then i want to check count is 7 or not thats it....once x==4 then i should not check for x==7
awaiting for ur response...

 

[dave_59]

Change the and's to or's

Anything else you forgot to tell us? With assertions you need to be very concise about your requirements.

 

[shahsanket24]

I have tried the same thing but its not at all taking that properties in consideration means not at all triggered ......

 

[hdlcohen]

hello to all..

i want to write assertion for following condition.
bit [3:0] x;
bit [5:0] count;
whenever x is 4 then i want to check count =7, whenever x=6 i want to check count=9,whenever x=7 i want to check count=11. please help urgently

Use either of these property operators
The case property operator has the following form: [1]
case ( expression_or_dist )
property_case_item { property_case_item }
endcase
property_case_item::=
expression_or_dist { , expression_or_dist } : property_statement
| default [ : ] property_statement

or the

if (expression_or_dist) property_expr1
else property_expr2
--------------------------------------------------------------------------
Ben Cohen, Design and verification expert (310) 997-2187
https://www.systemverilog.us/ ben@systemverilog.us
* SystemVerilog Assertions Handbook, 2nd Edition, 2010 ISBN 878-0-9705394-8-7
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
* Component Design by Example, 2001 ISBN 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
--------------------------------------------------------------------------

 

[shahsanket24]

can u please tell me the same thing using my question....?