hello to all..
i want to write assertion for following condition.
bit [3:0] x;
bit [5:0] count;
whenever x is 4 then i want to check count =7, whenever x=6 i want to check count=9,whenever x=7 i want to check count=11. please help urgently
Use either of these property operators
The case property operator has the following form: [1]
case ( expression_or_dist )
property_case_item { property_case_item }
endcase
property_case_item::=
expression_or_dist { , expression_or_dist } : property_statement
| default [ : ] property_statement
or the
if (expression_or_dist) property_expr1
else property_expr2
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Ben Cohen, Design and verification expert (310) 997-2187
https://www.systemverilog.us/ ben@systemverilog.us
* SystemVerilog Assertions Handbook, 2nd Edition, 2010 ISBN 878-0-9705394-8-7
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
* Component Design by Example, 2001 ISBN 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
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