[systemverilog] about input skew in clocking block

[reasly]

Hi,
I have a question about the clocking block in systemverilog.
According to IEEE 1800-2005, the "input skew" specifies the time between the sample point and the clock edge. I tried the following code:

`timescale 1ns/1ps

interface if_dut(input logic clk);
    logic [5:0] counter;
    logic rst;
    clocking cb @(negedge clk);
        default input #1ns output #1ns;
        input  #1ns counter;
        output #1ns rst;
    endclocking
endinterface

module my_module(input clk,output [5:0] counter,input rst);
    reg [5:0] cnt;
    initial cnt=0;
    assign counter = cnt;
    always @(negedge clk)
      if (rst) cnt <=0;
      else cnt <= cnt+1;
endmodule

module tb_top;

    reg clk;
    initial begin
        clk = 1;
        forever #5 clk = ~clk;
    end
    
    if_dut dut_if(clk);
    my_module dut(.clk(dut_if.clk),
                  .counter(dut_if.counter),
                  .rst(dut_if.rst));

    initial begin

        dut_if.rst = 0;
        repeat(5) @(negedge clk);
        $display("[%t]cb.counter = %d",$time,dut_if.cb.counter);
        $display("[%t]   counter = %d",$time,dut_if.counter);
        repeat(5) @(negedge clk);
    end
endmodule

in the code , the cb.counter should be sampled 1ns before the clock edge, making the two display line print the same result, right?

However if simulated with vcs or ncverilog, I got different result.

can any one help explain why? thanks!