systematic offset voltage constraint for designing two-stage opamp

[bharat_tangudu]

I have a question regarding the systematic offset voltage constraint for designing two-stage opamp.

While designing the Two-stage op-amp, there is a relation to avoid the systematic offset voltage which can be defined for the given op-amp as,



((W/L)4)/((W/L)7)=0.5((W/L)5)/((W/L)6)

What happens if we don't follow this relation? I am asking this question because I am unable to satisfy this relation while designing op-amp.

In other words, Is it okay if our design won't satisfy this relation?

 

[dick_freebird]

That's a pretty simplistic formula even for a simple op
amp, the lambda / Early voltage (affecting the second
stage differently than the first stage NMOS) doesn't
appear. Likewise the Q5 / Q6 actual currents are bent
by different Vds.

The equation expresses the first order, ideal current
density balance-point for "ideal" MOSFETs. If you are
working in a technology where the FETs are anything
like "ideal", you're a dinosaur (and trust me, I know
dinosaur).

So take the equation as a (very) rough guide at best.
Spend some time figuring out exactly why it's letting
you down, it may still be telling you something (like,
beware optimizing too hard against nonideal device
behaviors, which never come out the exactly the same
as predicted; make sure you aren't running devices
too starved or too hot, such that nonidealities are
magnified; etc., etc.). Learn -why- your op amp has
to "break the rules", lest you break the wrong ones.

 

[bharat_tangudu]

That's a pretty simplistic formula even for a simple op
amp, the lambda / Early voltage (affecting the second stage
differently than the first stage NMOS) doesn't
appear. Likewise, the Q5 / Q6 actual currents are bent
by different Vds.

The equation expresses the first order, ideal current
density balance-point for "ideal" MOSFETs. If you are
working in a technology where the FETs are anything
like "ideal", you're a dinosaur (and trust me, I know
dinosaur).

So take the equation as a (very) rough guide at best.
Spend some time figuring out exactly why it's letting
you down, it may still be telling you something (like,
beware optimising too hard against the nonideal device
behaviours, which never come out the exactly the same
as predicted; make sure you aren't running devices
too starved or too hot, such that nonidealities are
magnified; etc., etc.). Learn -why- your op amp has
to "break the rules", lest you break the wrong ones.

Thanks for the reply. I took this relation as a rough guide only to design the structure and got this relation for above kind of op-amp. But I am trying to design the fully differential two-stage opamp. For this, I was not able to achieve that systematic offset relation

see the structure along with W/L ratios.

 

[dick_freebird]

That relation only attempts to "boil down" how to
make the output device OP match the diff pair OP
to achieve good Vgs match and eliminate that
element of systematic offset.

Now, the FD design you show looks prone to suffer
from imbalance between P and N current source
racks, which would need a common mode feedback
to address. You have two "lambda" error terms to
take out and your device lengths are that large.
Might play with offsetting the N load relative to the
P sources on the diff pair (and since you have flipped
front end, N for P, be sure you respect the very
different input common mode range).

 

[bharat_tangudu]

CMFB part is missing in this FD structure which I know and I am working on that. Can u elaborate what was the next point you are explaining


"You have two "lambda" error terms to
take out and your device lengths are that large.
Might play with offsetting the N load relative to the
P sources on the diff pair (and since you have flipped
front end, N for P, be sure you respect the very
different input common mode range)."

I modified the aspect ratios and able to put all the transistors in the saturation region.

 

[dick_freebird]

This amplifier won't work without at least one of
the NMOS front end devices' gates at >VT(N). Unlike
the PMOS front end amp originally shown, which might
work down to the negative / ground rail.

Should be "...aren't that large". You transfer the bias
current up from the N rack, incurring a lambda error there
(so reference current to the P rack > what's in the diff
pair due to headroom compression) and then the P sources
add their own error to the extent that their drain voltage
exceeds Vgs(M11).

Are you looking at OP drain currents in the bias network?

 

[jwcircuit]

Most of time, it is ok. But, just watch out not to have too much systematic offset. This video, https://youtu.be/0muVEGz5wZE
, shows what happens if you do not follow that. The trick is to increase the first stage gain to mitigate the issue. If the gain of the differential input stage is high enough, let us say 50dB+, most probably you do not have to follow that relation.

 

[bharat_tangudu]

Now I have come up with the complete fully differential opamp along with common mode feedback network.

I don't know whether my design is right or not.

But I am not able to keep all the MOSFETs in the design in the saturation region.

 

[dick_freebird]

You can't expect to keep -all- MOSFETs in saturation - the
ones connected D-G by definition, others due to headroom
at one end of common mode range or another, folded
cascodes seldom have the masters well saturated (only
the guards) and so on. Spend your efforts on the ones that
are gain-critical (and on knowing which).

I can't recall ever seeing 50dB of single stage gain (let
alone on a diff pair) - not reliably, across corners, with
devices modeled realistically. Yes, front end differential
gain knocks down input referred systematic errors. But
you can't put total hope on the front end, you still have
to make the single ended stages (and the back end is
almost always two single ended stages, phase-split)
offset-benign by balance and match (and maybe other
techniques as allowed, like chopping and zeroing, but
these are not true continuous-time and add their own
spectral issues).

 

[bharat_tangudu]

Thank you very much for the reply.
I have two questions to ask. Can you please answer my questions?

1) Where can be the CMFB placed in two stage fully differential opamp? (Like between the first stage output and gate terminal of current source load of the first stage OR second stage output and gate terminal of current source load of the first stage)

2)what's front end and what's back end that you are using you in your replies?