systematic offset for differential pair

[Rainbow00]

systematic offset

Hi,
can someone illustrate the concept for the input systematic offset for differntial pair? let's say for 1mV input systematic offset does it mean when 1mV is applied to the differential pair the output is biased at half of Vdd and Vss?

regards
gd

 

[rfsystem]

differential pair offset

Your are right. If VDD/2 is the target point. The systematic offset happen at the conversion between differential to single ended processing. Mostly the output mirror have a voltage difference between the MOS mirror diode input and the mirror ouput voltage. Try to use a topology where the mirror output have equal voltage as the mirror input. Then the systematic offset is reduced.

 

[yaxazaa]

systematic offset voltage

This is due to topology of you different, the conecpt means that to make output at common mode, the input need offset