common gate comparator offset

[bagan]

hi,

If VB is fixed voltage, and VA > VB, output Vx will change from low to high.

The input offset error primary determined by mismatch of IB for both branch and also the size of transistor MP1 & MP2. IB can be implemented using cascode current mirror to increase its impedance and the size MP1 & MP2 can be made large to reduce VGS mismatch.

My question is how to check the input offset error for this kind of amplifier in simulation?
Thank you very if someone can clear my doubt here. .

 

[dick_freebird]

That schematic is not the amplifier, but the easiest way to get a
Vio value is to put your amplifier in closed loop A=1, position the
input and output inside the recommended common mode range,
and take the difference (either post-run math, or a vcvs to make a
ground-referred V_vio signal you can print / plot directly.

 

[solidstate]

You can apply a voltage ramp to Va-Vb and record at which voltage the output toggles.
You could consider adding a second stage. That allows you to keep the MP1 and MP2 drain voltages equal throughout, which will help with (systematic) offset and hysteresis.