Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 entity OEncoder_1 is Generic (K : integer range 0 to 10 :=4; -- K bits for Message N : integer range 0 to 20 :=7); -- N bits for Codeword Port ( UTemp : in STD_LOGIC; SentU : out STD_LOGIC; Clk : in STD_LOGIC); end OEncoder_1; architecture Behavioral of OEncoder_1 is --Component Declaration Component D_FF Port ( D : in STD_LOGIC; CLK : in STD_LOGIC; Q : out STD_LOGIC; rst : in STD_LOGIC); end Component; --Signal Declaration Signal GP : STD_LOGIC_VECTOR ((N-K) downto 0) :="1101"; -- Generator Polynomial Signal i : integer range 0 to (N-K) := 0; -- Index on GP's Bits Signal j : integer range 0 to (N-K) := 0; -- Index on IOX Signal IOX : STD_LOGIC_VECTOR ((N-K) downto 0) :="0000"; Signal GTemp : STD_LOGIC; Signal Disable : STD_LOGIC := '1'; type Switch is ( SC , OC ); -- Short circuit and Open circuit Signal SW : Switch := SC; begin Process (CLK) Begin if( CLK'event and CLK ='1') then if(i < (N-K)) then if(GP(i) = '1') then U1: D_FF port map(D =>(Gtemp xor IOX(j)) , CLK=>Clk, Q=>IOX(j+1) , rst=>Disable ); else U2: D_FF port map(D => IOX(j) , CLK => CLK , Q =>IOX(j+1) , rst => Disable ); end if; i <= i + 1; j <= j + 1; else if(SW = SC) then Gtemp <= IOX (N-K) xor Utemp; SentU <= Utemp; else -- SW = OC Gtemp <= '0'; SentU <= IOX(j); end if; end if; end if; End Process; end Behavioral;
3- Yes i am sure. N & k have to be generics.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 entity OEncoder_2v2 is Generic (K : integer range 0 to 10 :=4;-- K bits for Message N : integer range 0 to 20 :=7-- N bits for Codeword); Port ( UTemp : in STD_LOGIC; SentU : out STD_LOGIC; Clk : in STD_LOGIC); end OEncoder_2v2; architecture Behavioral of OEncoder_2v2 is --Constant Declaration Constant GP : STD_LOGIC_VECTOR ((N-K) downto 0) :="1101"; -- Generator Polynomial --Signal Declaration Signal D,Q : STD_LOGIC_VECTOR ((N-K-1) downto 0) :=(Others => '0'); -- Flip flop's Inputs Signal ClockCounter : integer range 0 to N; Signal GTemp,UQX : STD_LOGIC; Signal Reset : STD_LOGIC := '1'; Type Switch is ( Parity , message ); Signal Switch2 : Switch := Message; begin -- taking care of FF's Input and XORs Gen1:for i in 1 to N-K-1 generate D(i) <= (Gtemp xor Q(i-1)) when GP(i)='1' else Q(i-1); end generate; D(0) <= Gtemp; -- taking care of FF's Outputs UQX <= Utemp xor Q(N-K-1); -- taking care of GATE Gtemp <= UQX when Switch2 = Message else '0'; -- taking care of Switch 2 SentU <= Utemp When Switch2 = Message else Q(N-K-1); -- Sequential part Process(Clk,Reset,ClockCounter) begin if( Reset = '0') then -- If #1 Q <= (Others => '0'); ClockCounter <= 1; Reset <= '1'; else -- Else #1 if (ClockCounter < N) then -- If #2 if(CLK 'event and CLK = '1') then -- If #3 Q <= D; ClockCounter <= ClockCounter + 1; if(ClockCounter = K) then -- If #4 Switch2 <= Parity; end if; -- End #4 else -- Else #3 NULL; end if; -- End #3 else -- Else #2 Null; end if; -- End #2 end if; -- End #1 end Process; end Behavioral;
This is the way you code a VHDL process that represents a bunch of FFs
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Process(Clk,Reset,ClockCounter) begin if( Reset = '0') then -- If #1 -- statements else -- Else #1 if (ClockCounter < N) then -- If #2 if(CLK 'event and CLK = '1') then -- If #3 -- else -- Else #3 -- end if; -- End #3 else -- Else #2 -- end if; -- End #2 end if; -- End #1 end Process;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 Process (Clk,Reset) -- Only Clk (and Reset if it is an asynchronous reset) begin if( Reset = '0') then -- reset values elsif rising_edge(Clk) then -- the rising edge function call will correctly deal with 'Z' -> '1', 'X' -> '1' etc transitions -- unlike the 'event code. Everything between this elsif and the end if is the synchronous stuff. if (ClockCounter < N) then -- do something while ClockCounter is < N else -- do this when ClockCounter is N end if; end if; end Process;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 entity OEncoder_3 is Generic (K : integer range 0 to 10 :=4;-- K bits for Message N : integer range 0 to 20 :=7);-- N bits for Codeword Port (UTemp : in STD_LOGIC; SentU : out STD_LOGIC; Clk : in STD_LOGIC); end OEncoder_3; architecture Behavioral of OEncoder_3 is --Constant Declaration Constant GP : STD_LOGIC_VECTOR ((N-K) downto 0) :="1101"; -- Generator Polynomial --Signal Declaration Signal D,Q : STD_LOGIC_VECTOR ((N-K-1) downto 0) :=(Others => '0'); Signal ClockCounter : integer range 0 to N; Signal GTemp,UQX : STD_LOGIC; Signal Reset : STD_LOGIC := '1'; Type Switch is ( Parity , message ); Signal Switch2 : Switch := Message; --Type Mode is (Idle, Encoding); --Signal Current : Mode := Idle; begin -- taking care of FF's Input and XORs Gen1:for i in 1 to N-K-1 generate D(i) <= (Gtemp xor Q(i-1)) when GP(i)='1' else Q(i-1); end generate; D(0) <= Gtemp; -- taking care of FF's Outputs UQX <= (Utemp xor Q(N-K-1)) When Utemp = '0' else (Utemp xor Q(N-K-1)) When Utemp = '1' else '0'; -- taking care of GATE Gtemp <= UQX when Switch2 = Message else '0'; -- taking care of Switch 2 SentU <= Utemp When Switch2 = Message else Q(N-K-1); -- Sequential part Process(Clk,Reset) begin if( Reset = '0') then Q <= (Others => '0'); Reset <= '1'; ClockCounter <= 0; elsif rising_edge(Clk) then Q <= D; ClockCounter <= ClockCounter + 1; if (ClockCounter = K) then Switch2 <= Parity; end if; end if; end process; end Behavioral;
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?