Advanced Member level 5
That is exactly correct.vGoodtimes
I have another question about this sentece that you mentioned earlier.
"RTL developers prefer to have modules with registered outputs and inputs when possible."
So you mean that I have to store Utemp (which is a serial input) in A FF first?
and then just use the FF instead?
it is like causing a delay (for one clock pulse)
is that what mean?
When designing FPGAs you usually dont care much about latency, as long as pipeline lengths are all matched. It's usually the throughput thats the most important thing.