SYSTEM VERILOG VERIFICATION ENVIRONMENT

[pradeep2323]

developing verification environment in verilog

Hi,

I have to develop a system verilog verification environment for my project.

could u plz help me out in this regards,and also provide some tool knowledge

and reffer some website form which i can download some materials.


regards,

Pradeep

 

[xuanzhu]

system verilog verification environment

if you use vcs as the simulator, you will find some examples in its doc directory, which are very helpful to you. Also, you can download the sv lab from the internet, which covers so many concepts in sv, such as coverage, mailbox, class, semaphore, etc.

 

[pradeep2323]

Hi,

Thank you for your reply.Presentely we are working on modelsim 6.2 version.
will it suitable for verification.

Regards,
Pradeep

 

[shobhitk]

Well Modelsim is good tool but VCS_MX is more sofiticated with System Verilog

 

[vicky3661]

questa tool is also good for system verilog. it supports AVM methodology.

 

[bywater]

Hi,

I have to develop a system verilog verification environment for my project.

could u plz help me out in this regards,and also provide some tool knowledge

and reffer some website form which i can download some materials.


regards,

Pradeep

Maybe you could call Synopsys's consultant to have a VMM concept before developing the verification environment. That will accelerate your project greatly.