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System Verilog in Magma

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hyy95120

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hi,
How can I import system verilog code in blastcreate?

using

import rtl xxx.v

report error message

On magma's web site, it said

"...Blast Create accepts RTL (Verilog, System Verilog or VHDL) or netlist input ..."

But I can't find any info from the online documents.


Please help!

Thanks!
 

kbulusu

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only new versions/builds released in Jan support SV and also they can just parse..they wont infer any logic..also they are supporting only assertions as of now...hope this helps...
 

spauls

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No you cant do for System verilog
 

aji_vlsi

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kbulusu said:
only new versions/builds released in Jan support SV and also they can just parse..they wont infer any logic..also they are supporting only assertions as of now...hope this helps...
Hi,
Does Magma support assertions for Synthesis? What does it synthesize to? I know DC "ignores" them - so simply parsing doesn't mean it "supports" it.

Regards
Ajeetha, CVC
www.noveldv.com
 

spauls

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Ajeetha ,
Magma also has some special switches for synthesis off for particular lines.
Assertions are very well defined under that sections.
 

aji_vlsi

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spauls said:
Ajeetha ,
Magma also has some special switches for synthesis off for particular lines.
Assertions are very well defined under that sections.
Hi,
So you are saying that if my assertions are inside "pragma"s (such as translate_on/off) - then Magma can handle it - that makes sense, in that case it simply doesn't even see that code.

Thanks
Ajeetha, CVC
 

kbulusu

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Ajeetha,
As I mentioned earlier..it doesnt synthesize to anything...EDA vendors normally add "support" in phases depending on the interests of customers...Right now, majority of the customers only use assertions and most of the designers and design managers whom I talk to are still reluctant to write synthesizable code in SV for variety of reasons...number one is most design houses want all their EDA vendors to be on the same level...since designers are using assertions for DV purposes ..it makes sense for EDA tool vendors atleast to have assertions support initially sothat they wont choke when it sees SV constructs...I hope this helps...ur book coauthored with Ben is good..

cheers kiran.

aji_vlsi said:
kbulusu said:
only new versions/builds released in Jan support SV and also they can just parse..they wont infer any logic..also they are supporting only assertions as of now...hope this helps...
Hi,
Does Magma support assertions for Synthesis? What does it synthesize to? I know DC "ignores" them - so simply parsing doesn't mean it "supports" it.

Regards
Ajeetha, CVC
www.noveldv.com

Added after 1 minutes:

yes magma can handle non propietary synopsys stuff...said that it can handle synopsys translate_off/on ...

aji_vlsi said:
spauls said:
Ajeetha ,
Magma also has some special switches for synthesis off for particular lines.
Assertions are very well defined under that sections.
Hi,
So you are saying that if my assertions are inside "pragma"s (such as translate_on/off) - then Magma can handle it - that makes sense, in that case it simply doesn't even see that code.

Thanks
Ajeetha, CVC
 

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