constfang
Newbie level 2
Basically, I was given a task to program the FPGA in an data acquisition board, the FPGA itself already contained the firmware of the board, so what I have to do is to program the "user logic" module. The rest of the firmware is closed source (but they do provide the interface for the user logic module).
Now, it'd be straight forward if I were going to program the module by Verilog, the problem is I don't have any experience with HDL language at all, so I'm considerring using Xilinx System generator (Sysgen). The problem is, I don't have any experience with Sysgen either (but I know that learning Sysgen is much easier than learning HDL), so I don't really know if Sysgen can be used in this case. So I'd like to ask if Sysgen can handle either of these following task:
- Program a single module with known interface and convert it to Verilog module file. Then I'd be able to put that file into Xilinx and build the whole project as usual.
Or,
- Import the closed source part of the XilinxISE project so that I can program the module in sysgen and build the whole project also by Sysgen.
I'd be very appreciate any help or comment. Thank you.
Now, it'd be straight forward if I were going to program the module by Verilog, the problem is I don't have any experience with HDL language at all, so I'm considerring using Xilinx System generator (Sysgen). The problem is, I don't have any experience with Sysgen either (but I know that learning Sysgen is much easier than learning HDL), so I don't really know if Sysgen can be used in this case. So I'd like to ask if Sysgen can handle either of these following task:
- Program a single module with known interface and convert it to Verilog module file. Then I'd be able to put that file into Xilinx and build the whole project as usual.
Or,
- Import the closed source part of the XilinxISE project so that I can program the module in sysgen and build the whole project also by Sysgen.
I'd be very appreciate any help or comment. Thank you.