Your question is incomplete. There are different kinds of constants which will synthesize differently. A simple constant input to a logic expression will be represented by a wire in RTL. But in synthesis, it's propagated into the logic and possibly causes a constant logic output, removing one or more logic elements. If you are talking about ASICs, there won't be a single superfluous gate with constant input, except for output drivers or elements created at will. In FPGA synthesis, you'll find many logic elements with constant input after mapping the design to gate level, but not necessarily the same as in the RTL description.
On the other hand, there are things like constant arrays that will be synthesized as ROM tables.