synthesizing functions in verilog

[krishanu007]

Hii all,
I have a function to implement & call it in parallel 5 times. So it has to perform 5 parallel calculations.
& The code needs to be synthesizable.:razz:
I am having doubt on "automatic" functions,they are mentioned in some tutorial websites to be used in case of recursive functions.
And automatic tasks are used in case of reentrant tasks.
Our need here is kind of reentrant fucntions..:roll:

please guide.

 

[rca]

used a loop with genvar, to generate your logic x times.

 

[krishanu007]

Thanks man,but I don' think you got the question.
suppose parity() is a function,
and If I write

assign a = parity(A);
assign b = parity(B);

and if I want it to be synthesized ,
do I need to add "automatic" in function declaration ??

 

[FvM]

There's nothing related to recursion in the example.

I wonder what you are actually asking?

 

[krishanu007]

Thats what..automatic is for reentrant tasks & recursive functions..(as far I know)
but this is a reentrant funciton..Some books are telling to use automatic in reentrant functions also.
But in their example they give recursive examples.

What I want is a synthesizable code with above example.
If it gives post-synthesis problem...I will be in problem.:lol:

 

[dave_59]

For time consuming tasks it matters , but pure synthesizable functions are not re-entrant because they execute in 0 time and do not save any state. Making them automatic will ensure at compile time that the function does not save or depend on any saved state.

 

[ads-ee]

Thats what..automatic is for reentrant tasks & recursive functions..(as far I know)

An example of why this is required...

Suppose you have a DUT with 2 identical interfaces. In your test bench you want to send data via a task to both interfaces. If you use a non-automatic task and try the following:

---

Code Verilog - [expand]
1
2
3
4
fork
  dut_port1.send_task (output1, output2, output3, input_clk);  // send task for dut port 1
  dut_port2.send_task (output1, output2, output3, input_clk);  // send task for dut port2
join

---

It won't work as both tasks will try to use the same set of internal task signals (I've accidentally had this happen when I forgot to add the automatic). By specifying automatic each call to the task from the two different dut port bus functional models will result in each task having it's own set of internal signals.

The same issue exists if a function is recursive as the function will be called multiple times in succession and will require that the state of anything in the function persist until after the next function call to itself is completed.

assign a = parity(A);
assign b = parity(B);

This example will simulate and synthesize correctly as the function parity for parity(A) will complete in 0 time anytime A changes. This will happen before the assignment to b occurs. Think of the function as inline code that executes as if you just wrote it out in place of the function (that's the reason why functions can't have any time control statements embedded in them).

Regards