1. You want to keep the clock period
2. You want to change the phase.
3. You only have the one clock.
I don't know of an RTL way to achieve this, but their are macros/cores within the IC device(FPGA I assume) that you can utilize as #2 mentioned
If you had a significantly faster clock, you could sample the slower clock. Delay it by so many fast clock cycles & that way it appears as if the cycle has shifted.
1. Take 10 MHz clock (100 ns period)
2. Invert it - you will get 2nd clock 10 MHz phase shifted by 180 deg.
3. Use Dff to divide those two signals by 2.
4. You will get two signals at 5 MHz (200 ns period) shifted by 90 deg -> that is 1/4th of cycle.
Use a delay element, which should be a FPGA primitive.
I also also don't know how to do it in RTL (if the last sentence in #3 cannot be applied).
Eg for a Xilinx 7 series FPGA, I would instantiate the IDELAY/ODELAY primitives to achieve the desired # amount.
200ns is so slow that you could use a third clock to define these two. you need a precision of 50ns only, which is still very slow even for older FPGAs.
If your clock periods were more challenging, PLLs would be the way to go.