[SOLVED] synthesizing a VHDL code with an IP core?

[Fractional-N]

Hi,
I have a VHDL code, and there is a FIFO ip core in the code. I have copied the .vhd files and .ucf files and also a .v file and ipcore_dir directory to another directory and I tried to synthesize the code but ISE gives the Error "Could not find module/primitive "
the code is a mixed VHDL and Verilog one.

what should I do? any help?

 

[barry]

You've apparently got some files in the wrong place. ISE is looking for them somewhere other than where you've put them.

 

[Fractional-N]

with trial and error, I solved the problem.
when configured a new project and added the source files, the IP core in the design had a VHDL icon at left-side like this:

then I selected this file and right-clicked and add source... and added the .xco file inside the ipcore_dir directory, then the icon changed to a lamp :

and the syntheses was successful