synthesizable delays...

[raja1982y]

Hi,

I am new to this group. I am new to design.

How can i design a module that consists of synthesizable delays. For example after assertion of "en" signals wait 2,3 or 4 clock cycles and then assert "strobe" signal. The delays are programmable. How can introduce the synthesizable delays between "en" and "strobe" signals.

Thanks,
Raja.

 

[rsrinivas]

u can use a counter to count the number of cycles desired and then assert or deassert the required signals.
No delays like #3 or wait are synthesizable.

 

[raja1982y]

if i have so many signals with different delays then there will be so many counters. If i synthesize the code there will be so many counters created. what about the performance of the module?

Thanks.

 

[megastar007]

There is no otherway than programmable counters.

 

[avimit]

Hi,
You need just one counter, preferably a counter that counts down instead of up. Then load your 'programable' delay value in this counter then, let it count down until it reaches 0. At 0 value, assert your strobe.
Hope it helps, let me know if it works for you, if not, then time permitting, I may be able to do a small code for you
Kr,
Avi
http://www.vlsiip.com

 

[raja1982y]

Is counters is the only way or there any other methods for implementing the synthesizable delays?

-Rj

 

[avimit]

Yes, Counter is the only way you are going to accomplish it.