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synthesizable delay-need help

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jis

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as it is not possible to produce synthesizable delay using "wait for " statement i wrote the following code. But it shows some error , I did'nt understand what the error was. i wrote the following code within the process statement.

process(clk)
variable count:integer;
begin
.
.
.
.
.
.
L1:loop
count:=count+1;
exit when count=1000000;
end loop L1;

For producing the delay I wrote the code snippet , which also produced the same error.

for i in range 0 to 1000000 loop
null;
end loop;

Pls help me in figuring out what the error is.
 

barry

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Maybe you could share your error with us, or should we just guess?

Your first bit of code L1:... will do nothing, since you are using a variable rather than a signal.

Your second bit of code will also do nothing, since you are TELLING IT TO DO NOTHING a million times.

It's a simple matter to just create a counter, preload it with some value, and decrement it until it reaches zero.
 

jis

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Dear barry,
in the first case i set up a counter , ie; i incremented it frm 0 to 1000000 and outside the loop i am reseting the variable to 0 so that it will do the same when it enters the loop next time. That is what I meant while writing the code. Incrementing a counter as well as decrementing the counter will produce the same effect right??also what is the difference, between manipulating a variable or a signal inside the loop, if my aim is just to produce a delay I am not using the value assigned to it anywhere else.And also even if null does nothing it wil help in elapsing the time, right.. pls correct me, if i am wrong.
 

FvM

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It looks like you learned a few Verilog constructs. But did you ever hear about basic concepts of hardware logic design? As barry mentioned, the shown code is useless both in hardware design or simulation because it neither generates any hardware nor a delay in simulation.

Delays in simulation can be inrodcuced by simple delay and other timing statements. Delays in hardware are generated by counting clock cycles. An external clock is required for it.
 

barry

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Your first case is not a counter, at least not in the hardware sense. When you assign a value to a variable it takes on the value instantaneously (as opposed to signals, which take on their value at the end of the process). You need, first, to understand how variables and signals differ. In your code the variable COUNT is give the value 1000000 every clock cycle; it DOES NOT increment every clock cycle. Essentially (but not in reality) COUNT increments from 0 to 1000000 every clock cycle; the synthesis tool will eliminate the logic you think you are creating.
 
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FvM

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HDL code like the present is often written when erroneously thinking about hardware logic as a microprocessor that needs several clock cyles for an instruction.
 
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jis

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Thanks it was really helpful. I thought the loop i wrote will produce delay in a manner similar to that of microprocessors or controllers.
 

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