andrew257
Member level 2
hi all,
is it possible to use the "+" in verilog language and expect the compiler to make the logic for an adder.
e.g
input a;
input b;
output c;
assign c = a + b;
is code like this synthesizable or would i actually have to look at making an adder from logic gates etc.
thanks
is it possible to use the "+" in verilog language and expect the compiler to make the logic for an adder.
e.g
input a;
input b;
output c;
assign c = a + b;
is code like this synthesizable or would i actually have to look at making an adder from logic gates etc.
thanks