Synthesis warnings in DC

Hi,

I am newbie to DC and to this forum, I have a warning after compile_ultra in my synthesis that says " Warning: Design 'abc_top' contains 1 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134)
Net 'freqdiv1/Reset': 1095 load(s), 1 driver(s)"

I am a student learning the tools, I am using SAED 90nm technology for my design, we have access to only limited options in student versions
Friends can you help me rectify this problem. I infer from many threads in the forum that I may have to use Set_driving_cell command, to increase the drive strength of my high fanout pin.but,

1. how to go about it??

2. do i have any option is synopsys DC tool to add a buffer in front of the input port??

Regards,
Harry potter

That's a reset port. You should use set_ideal_network command in DC for the signal. It is normal synchronous reset have many fanout because it is connected to many flops.

Thanks.

Like clock tree synthesis, Reset tree also built by Physical design tools. Either you can ignore this warning (only if its reset port). or use below command to get rid of this.

set_ideal_network [get_port *reset_ports*]

You need to specify the driving cell for the input ports.

set_driving_cell [get_buffer */BUF*] [get_port <your port names].


there are many Synopsys training materials avaialble. Google it. u get plenty for free.

Regards, Sam

Thank You, I will try

Regards,
Harry