Synthesis & STA: clock network timing definitions

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ivlsi

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Hello All,

How a clock timing should be defined during synthesis/STA? I mean skew/uncertainty/latency parameters. Should they be defined differently for the BC and WC checks?

Thank you!
 

Actually while setting the uncertainty value there is option -max and -min by which u can specify wc and bc respectively.
 
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    ivlsi

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pavanks said:
Actually while setting the uncertainty value there is option -max and -min by which u can specify wc and bc respectively.
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What's about input/output delays? Do they also have min/max definitions?
 

If you are using PT tool , then its better to use " man " command followed by required command to get whole information about it. It would be more accurate , with all options and how / where to use commands.
 

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