Synthesis & STA: clock network timing definitions

[ivlsi]

Hello All,

How a clock timing should be defined during synthesis/STA? I mean skew/uncertainty/latency parameters. Should they be defined differently for the BC and WC checks?

Thank you!

 

[pavanks]

Actually while setting the uncertainty value there is option -max and -min by which u can specify wc and bc respectively.

 

[ivlsi]

Actually while setting the uncertainty value there is option -max and -min by which u can specify wc and bc respectively.

What's about input/output delays? Do they also have min/max definitions?

 

[honey13]

yes, they too have max and min options

 

[jeet_asic]

If you are using PT tool , then its better to use " man " command followed by required command to get whole information about it. It would be more accurate , with all options and how / where to use commands.