synthesis report help

[Mina Magdy]

please i want to know was that synthesis report is using only 4% of the Flip flop or it use 66%

Slice Logic Utilization: 
 Number of Slice Registers:            9113  out of  607200     1%  
 Number of Slice LUTs:                202346  out of  303600    66%  
    Number used as Logic:             202346  out of  303600    66%  

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:  202381
   Number with an unused Flip Flop:   193268  out of  202381    95%  
   Number with an unused LUT:            35  out of  202381     0%  
   Number of fully used LUT-FF pairs:  9078  out of  202381     4%  
   Number of unique control sets:      9006

IO Utilization: 
 Number of IOs:                           4
 Number of bonded IOBs:                   4  out of    700     0%  

Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------

thanks in advance

 

[TrickyDicky]

Whats the question? It looks like you have a very very asyncronous design.

 

[Mina Magdy]

this is my code if you could help it will be greatfull

data_counter=data_counter+1;
				
				if(data_counter < 7200)
				begin
				
					if(bit_counter == 359)
					begin
						bit_counter=0;
						row_counter=row_counter+1;
					end
					else
						bit_counter=bit_counter+1;
			 
					if(row_counter < 5)
						no_bit=8;
					else
						no_bit=3;
						
					data=data_in;
					data_out=data;
					j=0;
					for(j=0;j<8;j=j+1)
					begin
						if((j<no_bit))
						begin
							address=table_1_2[j];
							temp= address + bit_counter * qldpc;
								if(temp>=9000)
								begin
									parity_address=temp-9000;
								end
								else
								begin
									parity_address=temp;
								end
							parity[parity_address]=parity[parity_address] ^ data;
						end
					end
					
				end
				else
				begin
					if(data_counter<16200)
					begin
						if((data_counter == 7200))
						begin
							parity_address=0;
							data_out=parity[parity_address];
							parity_temp=data_out;
						end
						else
						begin	 
							parity_address=parity_address+1;
							data_out=parity[parity_address]^parity_temp;
							parity_temp=data_out;	
						end
					end	
				end

 

[TrickyDicky]

helpo with what?

 

[Mina Magdy]

to decrease the number of used FF
what should i do?

 

[mrflibble]

You have a shitload of used LUTs, but only a small fraction of FFs. So you just /think/ you are using a lot of FFs, but you are not. Incidentally, have you checked how many levels of logic this generates? I suspect it's going to be more than a few... I would worry more about the logic levels, and less about the number of flip-flops used.

 

[Mina Magdy]

You have a shitload of used LUTs, but only a small fraction of FFs. So you just /think/ you are using a lot of FFs, but you are not. Incidentally, have you checked how many levels of logic this generates? I suspect it's going to be more than a few... I would worry more about the logic levels, and less about the number of flip-flops used.

ok thanks alot for your replay
i want to know did you mean that i only use 3% (4%*66%) of the available LUT-FF

 

[mrflibble]

Number of Slice Registers: 9113 out of 607200 1%

So not even 3%.

 

[barry]

I don't know verilog, but as Tricky has said, it looks like you are trying to create some counters without using a clock. Sounds like a very, very bad idea to me.

 

[Mina Magdy]

I don't know verilog, but as Tricky has said, it looks like you are trying to create some counters without using a clock. Sounds like a very, very bad idea to me.

thanks barry this is only a part of code

 

[barry]

Not really sure what you want to do here. You are using a tiny amount of the available FF, yet you want to reduce that? Can I ask why?

And posting partial code and then asking us to tell you why you get some specific result is impossible to do.