synthesis report generation taking long time to vhdl code in xilinx?

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sivaprasad007

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Iam studying btech final year,iam doing my project work on aes-128 algorithm implementation on fpga,i was able to simulate and get result .
but when i was about to synthesis it ,in order to dump it in fpga,it is taking long time to generate report, i dont know what might be the problem,

can any one suggest me your views...please

thank you...in advance
 

Synthesis duration Depends
on

1. VHDL Design
2.Processor /Memory etc ...

some times wrong hardware descriptions makes synthesis time too large

If your report has something like this ....




you need to change the code ...


if you can provide the following info
target FPGA
system configuration
 
Compilation can take a long time, depending on your design. Like blooz says, one of the biggest culprits is infering massive register arrays when you actually wanted a ram.
 
Boss ,actually when i was synthesising,no such type of message displayed,but it is running only.......continuosly.....no warnings...no errors....
please do help me if you got the mistake known..

IF the code length is high, synthesis problem occurs like that?
my code length is tooo big (5 modules,totally 1500 lines like that)
 


1500 lines doesn't imply a big deal .

Xilinx ISE /Altera Quartus message window===>there you can see some valuable information
 

its the code that the is the problem, not the volume.
Can you post a code snippet?>
 

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