KHDAK
Junior Member level 1
Hi,
I have technology library for 2048x32 RAM and I want to use it with my VHDL design in Cadence RTL compiler. This library contains *.lib flies and VHDL simulation model. When I include this RAM as a component in my VHDL code the RTL compiler interpret it as a black box. Do I need a VHDL file for this RAM or is it fine to just define it as a component in my code?
I have technology library for 2048x32 RAM and I want to use it with my VHDL design in Cadence RTL compiler. This library contains *.lib flies and VHDL simulation model. When I include this RAM as a component in my VHDL code the RTL compiler interpret it as a black box. Do I need a VHDL file for this RAM or is it fine to just define it as a component in my code?