Synthesis of RAM in Cadence RTL

[KHDAK]

Hi,

I have technology library for 2048x32 RAM and I want to use it with my VHDL design in Cadence RTL compiler. This library contains *.lib flies and VHDL simulation model. When I include this RAM as a component in my VHDL code the RTL compiler interpret it as a black box. Do I need a VHDL file for this RAM or is it fine to just define it as a component in my code?

 

[rca]

You do not need a VHDL file for the ram, just a liberty for this ram.
And a libert for the std cell.

 

[KHDAK]

ok but I am getting a message that RAM component is inferred as a logic abstract and I also can't see that logic inside RAM block in schematic view.

 

[rca]

You should not see any logic inside the RAM is this one has a liberty associated.

 

[KHDAK]

Thanks rca