Try with code and let me know results
module Traffic_light_controller(
input clk,
input rst,
output reg R1, // East Red
output reg O1, // East Orange
output reg G1, // East Green
output reg R2, // West Red
output reg O2, // West Orange
output reg G2, // West Green
output reg R3, // North Red
output reg O3, // North Orange
output reg G3, // North Green
output reg R4, // South Red
output reg O4, // South Orange
output reg G4 // South Green
);
parameter [2:0] state_1= 3'b000;
parameter [2:0] state_2= 3'b001;
parameter [2:0] state_3 =3'b011;
parameter [2:0] state_4 =3'b110
parameter [2:0] state_5 =3'b100;
reg [2:0] state,next;
reg [5:0] count;
initial count=6'b000000;
always @(posedge clk)
begin
if(rst)
count<=6'b000000;
else if(count==6'b011111)
count<=0;
else
count<=count+1;
end
always @(posedge clk)
begin
if (rst)
state<=state_1;
else
state<=next;
end
always @(rst,state,count)
begin
R1=1; R2=1; R3=1; R4=1;
O1=0; O2=0; O3=0; O4=0;
G1=0; G2=0; G3=0; G4=0;
case (state) // Line 75 on which it is giving message
state_1: begin
if(rst)
begin
R1=1; R2=1; R3=1; R4=1;
O1=0; O2=0; O3=0; O4=0;
G1=0; G2=0; G3=0; G4=0;
next<=state_1;
end
else
begin
next<=state_2;
end
end
state_2: begin
if(count>=6'b000000 & count<=6'b000101)
begin
R1=0; R2=1; R3=1; R4=0;
O1=1; O2=0; O3=0; O4=0;
G1=0; G2=0; G3=0; G4=1;
next<=state_2;
end
else if(count>=6'b000110 & count<=6'b000111)
begin
R1=0; R2=1; R3=1; R4=1;
O1=0; O2=0; O3=0; O4=0;
G1=1; G2=0; G3=0; G4=0;
next<=state_2;
end
else
begin
next<=state_3;
end
end
state_3: begin
if(count>=6'b001000 & count<=6'b001101)
begin
R1=0; R2=0; R3=1; R4=1;
O1=0; O2=1; O3=0; O4=0;
G1=1; G2=0; G3=0; G4=0;
next<=state_3;
end
else if(count>=6'b001110 & count<=6'b001111)
begin
R1=1; R2=0; R3=1; R4=1;
O1=0; O2=0; O3=0; O4=0;
G1=0; G2=1; G3=0; G4=0;
next<=state_3;
end
else
begin
next<=state_4;
end
end
state_4: begin
if(count>=6'b010000 & count<=6'b010101)
begin
R1=1; R2=0; R3=0; R4=1;
O1=0; O2=0; O3=1; O4=0;
G1=0; G2=1; G3=0; G4=0;
next<=state_4;
end
else if(count>=6'b010110 & count<=6'b010111)
begin
R1=1; R2=1; R3=0; R4=1;
O1=0; O2=0; O3=0; O4=0;
G1=0; G2=0; G3=1; G4=0;
next<=state_4;
end
else
begin
next<=state_5;
end
end
state_5: begin
if(count>=6'b011000 & count<=6'b011101)
begin
R1=1; R2=1; R3=0; R4=0;
O1=0; O2=0; O3=0; O4=1;
G1=0; G2=0; G3=1; G4=0;
next<=state_4;
end
else if(count>=6'b011110 & count<=6'b011111)
begin
R1=1; R2=1; R3=1; R4=0;
O1=0; O2=0; O3=0; O4=0;
G1=0; G2=0; G3=0; G4=1;
next<=state_4;
end
else
begin
next<=state_2;
end
end
default : begin
R1=1; R2=1; R3=1; R4=1;
O1=0; O2=0; O3=0; O4=0;
G1=0; G2=0; G3=0; G4=0;
end
endcase
end
endmodule