please show us what's the fatal error.
I don't advice to use 64-bit version.
Try command:
compile -incremental
Yes, I too had such issue with set_max_leakage_power, set_max_area constraints.Fatal errors occur when you have some strong problem in design. Actually it could be anything: area or time violations, wrong op conditions and so on. If all steps before "compile" have no issue, try to change compile strategy: start with launching without any constraints, and if it's good, add constraints gradually.
vijay.mani884, which memory options has DC? I know that exist multithreading options (set_host_options -max_cores, compile -num_cores), but in modern versions DC this feature executes automatically.
Yes, I too had such issue with set_max_leakage_power, set_max_area constraints.
1: dc_shell-t -64
2: use server with more physical memory.
Are you using a script for compiling or you manually implement it on Design Vision? In fact, some sophisticated designs can run faster 2-3 times if you're using scripts.
Fatal errors occur when you have some strong problem in design. Actually it could be anything: area or time violations, wrong op conditions and so on. If all steps before "compile" have no issue, try to change compile strategy: start with launching without any constraints, and if it's good, add constraints gradually.
I wonder, is there any way to make DC give full response about fatal error, without this useless information about support.
Hello,
First of all try and give the memory option for the tool. Check with your senior for the command for allocating memory, may be your design is not getting the sufficient memory for performing the synthesis.
Cheers.
Well, i think you should do a work around. do you have any other dc version available at your workplace? if yes, try and use that. as far as the command is concerned, i shall try and give you that. I need check it first.
Cheers
Hi,
You could tried without any sdc constraints, without any specific optimisations option, and execute one elaboration and synthesis. If that is ok, add one by one option and constraints.
Hi,
You could tried without any sdc constraints, without any specific optimisations option, and execute one elaboration and synthesis. If that is ok, add one by one option and constraints.
Could you removed the knowned options perhap, this design with this option could make this scratch?
Did you have a FPGA tool suite like quartus2 (free)? With this you could check your codes is correct, by executing a synthesis on your code.
Or if you access to an other synthesis tool?
I means your script, only read the source code, and two commands, elaborate, synthesis, that's it.
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If your code is correct, in this case, you need to change the tools version, or and check the know issues of this tool version in solvnet.
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