Synthesis--> Generic cell library

[NITIN BHARDWAJ]

Hello All,
Do we have any kind of timing information in generic cell library(G.tech ,chipware).If not then why results of synthesize to_generic changes(in terms of timing slack,area and number of instances) if we read two different SDCs before this command.

Regards
Nitin

 

[mohaddin]

Hi

Please refer DC manual for this

Regards
Mohi

 

[no_mad]

Hi Nitin,

Why do you want to synthesis using generic lib?

In my opinion, generic lib is not a technology library. Means, it does not give you the correct timing information.
You cant use this generic lib to synthesis and perform STA.

What do you need is a real tech library. Ex. tsmc or ami.

 

[funzero]

there is no timing infomation in generic library. it is used to translate rtl logic to gate level . after mapping to real library, you can get timing info.