I have run DC. There were no error in my reports but there were a lot of warnings. I have attached some of the screenshots in my "check_design" report. Is this the reason why my formality test failed? If so, how can I reduced or eliminate the problem.
For one thing, it looks like you've got outputs connected to outputs. Not sure why that's only a warning and not an error. But I think you need to fix the problems that are causing the warnings if you don't want to see them...
barry I don't think the report is showing that outputs are shorted together.
The report is saying you have an output port that is driven by a logic 1, i.e. the source of the output port is a logic 1.
I also think there might be a connection problem on the alu_stat_wr[2] and alu_stat_wr[3] that needs to be looked at. Maybe the same statement is driving both ports.
Im not sure where you see this - but this is not a problem. Often, 1 bit vectors come about when you have a component with a port sized by a generic (or it is generated code) and the size is set to 1.