Synthesis a synchronizer circuit

[no_mad]

Hi all,

In my design, I used 2 flip-flop synchronizer as a countermeasure for metastability.

During my top module synthesis, DC and PT prompt a hold time
violation between these 2 flip-flop.

If I use DC command “set_fix_hold clk1”, DC will add buffers to this path.

The question is:
Is it correct? Or I just leave it to layout guys to fix hold time violation for my synchronizer circuit.

Please enlighten me.

Thanx in advance,

 

[nittinsharma80]

Hi,
You can work either way i.e. ask DC to remove hold time problems by adding buffers or ask the layout guys to do it for you. both aproaches are right.
However the hold violation removal at layout stage is more common. They will size the transistors of your synchronizers such that the hold violations get resolved

 

[Thomson]

according to my design experience, there shall be no logic between the synchronizer and the signal from one clock field to the synchronizer.


and this syncrhonizer logic shall be as a black box and shall not be altered during the later phase!

you can change the timing checking in the ultimate SDF file to the corresponding DFF. this is the easiest way to realize the dynamic simulation!\]