Are there any scripts out there to convert between synopsys constraint scripts and synplicity constraint scripts?
Also, it seems there is not a direct way to specify combinational delays (ie set_max_delay) in synplicity. Is this true? Must I use a referece to a virtual clock?
Defining Clocks
...
5.Define internal clock frequencies (clocks generated internally) with the define_clock constraint. Apply the constraint according to the source of the internal clock.
Source : Comb. logic
Apply define_clock to... : Net. Make sure to use the n: prefix in the SCOPE interface.
regards,
Buzkiller.
<font size=-1>[ This Message was edited by: buzkiller on 2002-04-03 02:21 ]</font>
Tried defining vertual clocks and assigning 0 input and output delays wrt the appropriate sigs. It seems the tool only looks at one clock and optimises for it. In this case vclockSlow. See constraints below:
I think that you can define only one virtual clock for design, but not sure about it. Change the order of virtual clocks in your .sdc file, and if this time "vclockFast" will be the chosen one, then I'm right.
Anyway, why do you want to set the exact constraints for these combinatorial paths ? It's allrignt to overconstraint your synthesis, as long you have the correct constraints for PAR.