tonelow
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Hello,
I am a (student) researcher working with Synopsys EDA software packages for the first time. I have successfully constrained and compiled a circuit benchmark with Design Compiler (and extracted back-annotated saif), PAR with IC Compiler ( and extracted parasitics), simulated switching behavior with VCS (forward annotated saif), and am currently analyzing timing and power with PrimeTime. I have many RC-004 warnings (same warning for different arcs) which I cannot find any documentation about and was hoping somebody could point out what I am missing. I am using Synopsys University 28nm Standard Cell Library and I am not sure what details to post, so I will first start with just the warning itself:
Warning: Failed to compute C-effective for the timing arc through port line2 (min-rising) because the library data indicates a non-positive drive resistance. [r/f inp_slew - 0/0, out_cap = 6.68228 (lib units) ]
Thank you,
Tony
I am a (student) researcher working with Synopsys EDA software packages for the first time. I have successfully constrained and compiled a circuit benchmark with Design Compiler (and extracted back-annotated saif), PAR with IC Compiler ( and extracted parasitics), simulated switching behavior with VCS (forward annotated saif), and am currently analyzing timing and power with PrimeTime. I have many RC-004 warnings (same warning for different arcs) which I cannot find any documentation about and was hoping somebody could point out what I am missing. I am using Synopsys University 28nm Standard Cell Library and I am not sure what details to post, so I will first start with just the warning itself:
Warning: Failed to compute C-effective for the timing arc through port line2 (min-rising) because the library data indicates a non-positive drive resistance. [r/f inp_slew - 0/0, out_cap = 6.68228 (lib units) ]
Thank you,
Tony