synopsys design ware help

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elvishbow_zhl

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dw02_mult_2_stage means there are one register in multiplier?
the difference between it and DW02_mult is only one pipeline? or 2 pipeline?
 

from the SNUG, it sound like that.
but i have to remind, since the auto retiming is support, there might be excessive stage registers for the partial product.

usually, we use explicit structure, like (Wallace Tree + Adder), which can help reduce the internal registers.

regards.
 

I think we should not rely too much on DW to optimize our circuit. If you want to pipeline the multiplier, just do it by yourself.
 

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