synopsys Design Compiler showing ran out of memory

[vijay kanchetla]

Hi all,

I'm using Synopsys design compiler to synthesize my design written in verilog HDL. while synthesizing DC tool is throwing a message as
"
The tool has just run out of memory:

Memory allocated = 3863 MB, Request size = 49152 bytes.

.....it displys some numbers here ....

Out of memory.
(Memory allocated = 3955760 K bytes)


"
I'm able synthesize all individual modules, But when I try to synthesize complete design, it shows the message and exits. I'm using system having 4gb RAM, redhat Linux (64-bit).

please suggest me the ways to resolve the issue.

thank you

 

[yadavvlsi]

when memory requirement goes up more than available RAM size. Tool tries to use swap memory. If this is also not sufficient tool runs out memory. You can try below option.
1. Increase swap size.
2. Synthesize your design in small parts.
3. Reduce optimization effort medium/low. If is set to high.
4. Use different coding style.. Some of the the constructs may take more memory.

 

[ads-ee]

1. Increase swap size.

Warning this will have severe impact on performance and will significantly slow down the synthesis run.

I'm able synthesize all individual modules, But when I try to synthesize complete design, it shows the message and exits. I'm using system having 4gb RAM, redhat Linux (64-bit). please suggest me the ways to resolve the issue.

I'd say you should add more memory to the machine.

If you look in the Synopsis DC documentation I'd imagine there are suggested memory requirements for a system based on some metric like number of gates.

Regards