linny_chen
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There is one command in synopsys design compiler called "set_case_analysis", which can set some constant test case on certain ports, without optimized away components influenced by this constant setting. But "set_case_analysis" can only set signal values like 0, 1, rising edge and falling edge to the test ports. Could anyone tell me if there is such similar commands which could set values like Z, -, U, X etc? Thanks a lot!