Hi,
(1) First you need to design your system using RTL(Verilog or VHDL). You can take these files in to modelsim and simulate it. For that first open modelsim and create a project and corresponding "work" directory to store your design files. THen you have to write a stimulus file namely stim.do and execute it on the modelsim command prompt. The stimulus file is something like this:
add wave list *
/$design_name/clock 0 0, 0 10, 1 20, 0 30 -r200
/$design_name/A 0 0, 1 5, 0 30
run -200
and so on for all inputs and outputs you want to monitor. Also test your design with Test benches.
(2) If everything works well, take that RTL file to Synopsys DC and compile it with the ASIC technology files supplied by the ASIC foundary Company like LSI logic or Kawasaki LSI etc.
You may also perform Lint checks and DFT checks using Synopsys DFT Compiler. The DC script commands can be found in DC tutorial from
www.deepchip.com (downloads).
(3) you can per form static timing analysis using Synopsys Primetime.
(4) Use LBIST for BIST cell and scan chain insertion. Then you can use the Floorplan manager or Avant Jupiter for Floor plan. For place and route, ClockTree Synthesis there is Avant Astro. Use Synopsys Star-RC_XT for parasitic parameter extraction. You will also need to prepare data for the Synopsys Milkyway database.
(5) Once you get timing closure, you will have to take the design to generate the GDSII file which will be used for layout and actual ASIC design by the Foundary.