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Synopsys. 2007.03-SP*

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shahal

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Guys

any one have any experience with synopsys DC 2007.03-SP*? Any one have any experience in registers being optimized out when they are not suppose to be optimized out? I have been hearing about this through the garpe vine and was wondering about the validity of this statement.

Thanks
 

shahal

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No just hearing rumours, so trying to verify it. Just got off a meeting with Synopsys, they deny it.
 

rakko

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I really don't think something as simple as this would have gotten by the synopsys QA team. Having said this it is normal for a synthesis tool to optimize away registers. This happens especially in pipline designs as long as design functionality remains the same. Also, it is possible for the tool to combine and re-time different stages in the design to save registers. Of course the obvious ones such as un-connected outputs and multi-driven wires.......
I personally think this is a rumor spread by Magma people.
 

shahal

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Yeah I think its rumor also. I checked with some other sources, no one has heard of it. Sorry if I alarmed anyone..
 

avimit

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Dear rakko,
If it was so sure that synopsys QA would not let it go, then why synopsys will recommend 'formal verification' of the netlist produced by design compiler? The whole idea of formality is to catch bugs in DC.
kr,
Avi
https://www.vlsiip.com
 

rakko

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I think the purpose of FV is to check the netlist aginst yout RTL code. It used to be that designs were simple and dynamic verification was used to catch post synthesis bugs. These days netlists are too complex and running all your verification suites on the netlist is too slow and just not practical anymore. So, one way to make sure the netlist is just as good as the RTL is to verify the RTL using all your verification tests and use FV to make sure netlist is identical to the RTL. So, I think the purpose is to gaurd against mistakes introduced by the designers such as accidentally deleting a few lines of the netlist while fixing timing violations by hand.

Don't get me wrong, I'm not saying synopsys is perfect but don't think they miss the very simple stuff.
 

arunragavan

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yes you are true. I seen some post on deepchip on 07.03 DC has lot of bugs in seq. opto.
 

armardu

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Of course the obvious ones such as un-connected outputs and multi-driven wires.......
I personally think this is a rumor spread by Magma people.
 

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