I have to design a digital hardware block to synchronize a slower data rate from a network to a processor(working at higher data rate)...how should I go about the design ? should i use a PLL for this purpose ?
or use a asynchronous fifo (address should be gray coded)
best regards
keerthivasan_bits said:
I have to design a digital hardware block to synchronize a slower data rate from a network to a processor(working at higher data rate)...how should I go about the design ? should i use a PLL for this purpose ?
Using the Asynchronous FIFO is the best option by having some handshaking signals as every time the fast data rate should not wait for slower data rate while reading