tnguyens said:In FPGA design, there is no DFT/Scan insertion so I am thinking to use the synchronous reset for all FF's. Have anyone seen any problems on this synchronus reset design in the FPGA devices ?
Thanks
echo47 said:Async reset is tricky to implement reliably, and sync reset consumes resources, so I almost never use external reset in my projects. The FPGA automatically initializes all flops during configuration. I design my logic modules so in case of some unexpected run-time upset, the logic naturally falls back into normal operation (instead of getting stuck in an invalid state).
I think what u mean is Async reset in each module, but these async reset signal is generated by a main clock manager which practices syncronous reset.Thinkie said:Use Async reset, but the reset signal to be synchronously generated.
This is quite different from a syncrhonous reset
s0shinde said:example code:
always @(posedge Clk or negedge Resetn)
begin
if(!Resetn)
begin
rstn <= 1'b0;
async_rstn <= 1'b0;
end
else
begin
rstn <= 1'b1;
async_rstn <= rstn;
end
end
Use this aync_rstn to reset the flops. For example:
always @(posedge Clk or negedge async_rstn)
begin
if(!async_rstn)
q <= 1'b0;
else
q <= d;
end
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