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Synchronous and asynchronous design in SOC encounter

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vlsitechnology

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What is the difference between synchronous and asynchronous design

IF we have two clocks in synchronous design then there will be a chance that my skew will not meet the design requirements after doing the optimization also then at that time how shd i optimize the design?
can anyone explain me?
 

gliss

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Synchronous systems are driven by clock networks. Asynchronous ones aren't. SOC has automated tools for timing analyzis and optimization. You can run these tools at different points in the flow. After clock tree synthesis you can perform optimization like moving blocks around and changing/adding clock buffers.

For example, if there is too much scew, you can replace and reroute the design, change the clock tree scheme, use different buffers/etc. When you do this optimization you possibly are using more area and more power,

Also, most good ASIC libraries include two times of buffers, one for general use and one specifically for clock signals, make sure you're using the appropriate ones.
 

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