Synchronizers on FPGA (more requirements)

[suquid29]

Same issue from last week, but exact requirements now

I want to imlement this very simple circuit on VirtexII-Pro:

When sampling asynchronous signal, you can enter metastability. In this simple
circuit, I sample both in clk and delayed clk. The delay time is actually t_ko=t_su+t_h, hence, one FF sampled correctly.

The problem is implementing the delay line.
According to VirtexII-Pro data sheet, t_su+t_h for general CLB is ~0.14 ns, depends on the speed grade, so i want to be able to implement a delay line with resolution of 0.01 ns. Is this possible??

According to the same doc, t_pd of LUT is ~0.23 ns, so cascade of NOT gates wont do it...

Thanks in advanced.

 

[rasj12]

hello.. read this paper

J. Kalisz, R. Szplet, and A. Poniecki, Field programmable gate array based
time-to-digital converter with 200-ps resolution, IEEE Trans. Instrum. Meas.,
vol. 46, no. 1, pp. 5155, Feb. 1997.

 

[AdvaRes]

Hi,
Here you find the paper:

 

[j_andr]

/.../i want to be able to implement a delay line with resolution of 0.01 ns.
Is this possible?/.../

no, it's not at least in xilinx/altera fpga;

/.../you can enter metastability/.../

to get rid of metastability problem you do not need such 'sophisticated'
delay line, btw I doubt - even if possible - the delay line will be a solution;
let's say you have your fine DL, how can you know which register [up or bottom
on your picture] has correct data to clock distance, in other words how
will you control the multiplexer ?
simple and effective solution of metastability are 2 FF is series,
if the first one 'sees' clock slope at the data transition area, it can
enter any: H or L and then after a short period of time it can go back
to previous level - this is the meaning of 'metastability';
to reject this unstability the second flip-flop samples the first FF output
with the same clock, if the clock period is longer then unstable phase
of flip-flop1 you have a clean logic level at the output of the second
register;

another story is moving data from one clock domain to the other,
what - may be - is your case, then use known technics like dual clock
fifo which costs some clock latency but is save and easy, instead fighting
with unrealistic delay line;
good luck;

Added after 24 minutes:

============
one more note: the example on your picture - you do not have to
calculate the delay so preciously, if you clock the second FF
with falling slope one of the register must have correct data-to-clock
timing if data and clock frequencies don't differ too much;
the problem is of course - which one?
--

 

[suquid29]

Thanks for your replies.

I know about the two-flop synchronizer. As a matter of fact i know about many kind
of synchronizers. The reason is that my project goal is to compare between various
methods to sync (performance, area, latency).

So... I still need to create delay lines in order to implement some of the synch.

Does someone have an idea of implementing delay with VirtexII-Pro, with high res?
Can I use somehow DCM as delay line? (couldn't figure it out from user guide)

Thanks.

 

[j_andr]

have you read DCM user guide/manual ?
as far as I remember it's possible to change phase shift of the out clock
dynamically;
on the other hand for your purpose: "Synchronizers on FPGA" all you need
is clk0 and clk90, eventually clk180 outputs of dcm;

Added after 18 minutes:

Can I use somehow DCM as delay line?
(couldn't figure it out from user guide)

I missed somehow this line ...
could you paste a link to the dcm user guide ?
I've spent ~15 min. on xilinx site and failed to find it, i'm stupid or they have
funny doc organization;

 

[suquid29]

Clarification: I need to be able to delay both clock and data with good res.

Can this be done by DCM??



VirtexII-Pro docs can be found at:
https://www.xilinx.com/support/documentation/virtex-ii_pro.htm

 

[suquid29]

According to the docs, DCM can delay only clocks.

What did you mean by perfect?