Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Synchronize random data with clock

Status
Not open for further replies.

scdoro

Member level 5
Member level 5
Joined
Jan 12, 2005
Messages
87
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,040
hi everyone,

Qn(a): Can anyone help me with this? I need to synchronize the clock together with asynchronous RS232 data. The clock must be capable of generating a (10khz-16.7khz) frequency and it must be continuously high for at least 50 microseconds before data can be transmitted?(See attachment below)

Qn(b): How do I sample each data bit at its’middle with respect to the falling edge of the Clock? (See attachment below)

Thanks.
 

mwmmboy

Full Member level 2
Full Member level 2
Joined
May 18, 2001
Messages
134
Helped
8
Reputation
16
Reaction score
2
Trophy points
1,298
Activity points
979
Synchronize something to something asyncronuous... It sounds strange..

Pls give more details..
 

nandopg

Full Member level 4
Full Member level 4
Joined
Apr 26, 2001
Messages
205
Helped
8
Reputation
16
Reaction score
3
Trophy points
1,298
Location
Over the Rainbow
Activity points
2,521
One way to do what you need is to use an Early-Late Gate, that can be implemented using either analog or digital circuitry.
You can find the description of this gate in the literature on Digital Communication and on a couple of papers online.

NandoPG
 

echo47

Advanced Member level 6
Advanced Member level 6
Joined
Apr 7, 2002
Messages
3,933
Helped
638
Reputation
1,274
Reaction score
90
Trophy points
1,328
Location
USA
Activity points
33,176
It looks like you simply need a UART receiver, so you don't need precise synchronization. The common technique is to somehow generate a clock (usually by dividing down a crystal oscillator) that runs 16 times faster than the bit rate. Now design some counter logic that waits for the beginning of the start bit, then delays 8 clocks (the middle of the start bit), and then begins sampling the data bits every 16 clocks thereafter until you've sampled all 11 bits. Then check to see if the 11 bits make sense (start=0, stop=1, parity=whatever).

The values 16 and 8 are mostly arbitrary. For example, you could choose 10 and 5 if that's more convenient for you.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top